I. Field
The present invention relates generally to electronics circuits, and more specifically to techniques for accessing a memory device.
II. Background
Wireless communication devices (e.g., cellular phones) are capable of providing various communication services such as voice and packet data. Newer generation wireless devices may also be capable of providing enhanced functionality and may be used as a personal digital assistant (PDA), a Web terminal, a computing device, and so on. As wireless devices become more complex and provide more functions and features, more computing power and larger memories are inevitably required. A large memory is typically needed to store program code and data used to support voice and/or data communication as well as other functions and features.
Various types of memory may be used for wireless devices, such as static random access memory (SRAM), synchronous dynamic RAM (SDRAM), and Flash. SRAM and SDRAM are volatile memories that lose the data stored therein once power is removed. SRAM and SDRAM can be accessed in a random manner, which is the manner most processors access memories for program code and data. SRAM and/or SDRAM are thus commonly used as the main run-time memory in wireless devices.
Flash is a non-volatile memory that can retain the data stored therein even after power is removed. NAND Flash, which is one type of Flash, is a high-density memory design and has certain advantages over other types of memory. In particular, NAND Flash has large storage capacity (e.g., one giga bits or more), good speed for continued memory access, and low cost. However, NAND Flash also has certain inherent drawbacks such as poor performance for random memory access. Consequently, NAND Flash is typically accessed in units of pages, one page at a time, with each page being of a particular size (e.g., 512 bytes).
As the cost of memories in wireless devices becomes more prohibitive, NAND Flash is a good candidate for use as the mass storage unit for these devices. However, because the structure of NAND Flash is not suitable for random access, program code cannot be executed directly from the NAND Flash. Instead, SRAM and/or SDRAM may be used to provide run-time storage for program code and data that need to be accessed in a random manner.
A memory architecture that incorporates both NAND Flash and SRAM/SDRAM is able to provide large storage capacity with random access at reduced cost. For a device having such a memory architecture, the program code may be loaded into the NAND Flash for permanent storage. Upon being powered on, the device performs a “boot”, which entails (among other things) transferring the program code from the NAND Flash to the SRAM/SDRAM. Since the program code may be large in size (e.g., several mega bits), the boot time may be quite long (e.g., on the order of seconds). Slow boot time can lead to user dissatisfaction and is especially undesirable for devices that may be powered off and on frequently, such as cellular phones.
There is therefore a need in the art for techniques to quickly access NAND Flash for data transfers.